Switching in integrated circuits is necessary in order to properly route data to and from different logic and arithmetic components on the integrated circuit. As the complexity of integrated computing circuits has increased, the need for more flexible switches allowing routing of data between a variety of components has increased. For example, high capacity switches are useful in programmable hardware such as field-programmable gate array (FPGA) technology where logic components may have interconnections that are changed based on a configured subset of logic components needed to perform a function.
Traditional switches have a history dating back to the physical N×N telephone switches of the last century, through multi-stage networks developed in the 1950s and leading to modern telecommunications routers. An N×N switch is capable of passing data between any one of a first plurality of N-directional input ports to any one of N-directional output ports. Portions of a router may be implemented all or in-part in FPGA and application specific integrated circuit (ASIC) logic.
A Clos network is a well-known method for building N×N cross point switches recursively (meaning that an n-input network is built from other m-input networks where m<n). A general 3-stage Clos network consists of an ingress, middle, and egress network of crossbar switches, with parameters r, n, and m to implement an N×N permutation network with N=r*n. Each ingress stage crossbar switch has m outlets, and there are m middle stage crossbar switches. There is exactly one connection between each ingress stage switch and each middle stage switch. There are r egress stage switches, each with m inputs and n outputs. Each middle stage switch is connected exactly once to each egress stage switch. Thus, the ingress stage has r switches, each of which has n inputs and m outputs. The middle stage has m switches, each of which has r inputs and r outputs. The egress stage has r switches, each of which has m inputs and n outputs.
Such networks may have different categories such as blocking, non-blocking, rearrangeable, etc. A network is non-blocking if m≧2n−1, meaning that a new connection may be made without tearing up any existing connection. If m>n, then the network is rearrangeable, but not non-blocking as a new solution may be found, but not without changing some existing connection or connections.
As explained above, cross point switches are prominent in data communications applications, both in packet based switching and in optical transport. However, in the case of programmable hardware, different applications often require different cross point structures as the different applications require variable numbers of logical components to be connected. In order to maintain the flexibility of programmable hardware, making any design decision to harden a cross point switch on an FPGA die is a difficult proposition to justify from a cost and usage perspective since such a hardened switch has to have the maximum connection capability in order to be used for the universe of applications the FPGA die may be configured for.
FPGA users may have applications that require a cross point switch to connect different components on the FPGA die to implement the applications. However, the switch composition between different user applications may be different, making a general hardened logic solution very difficult to adapt to the various user needs. For example, one user may require 64 ports with each port being 100 bits wide. In contrast, a second user may require 16 ports each being 400 bits wide. The two users both require a cross point switch with the same number of inputs and outputs. A hardened solution that satisfies both user requirements is very difficult to build. Such a conventional hard logic solution would require building a cross point switch at the maximum parameters wanted by either user e.g., 64 ports at 400 bits wide for each port. Such a design satisfies the needs of both users, but increases the cost and complexity of the device.